This application claims priority from Korean Patent Application No. 2002-77033, filed on 5 Dec. 2002, in the Korean Intellectual Property Office, the contents of which are incorporated herein in their entirety by reference.
1. Field of the Invention
The present invention relates to a simultaneous bi-directional (SBD) buffer, and more particularly, to a simultaneous bi-directional (SBD) buffer including a self-test circuit having a function of generating an input signal and a self-testing method of the SBD buffer.
2. Description of the Related Art
As semiconductor devices operate at higher and higher speeds, perform more functions, and become more highly integrated, an operating frequency, a channel bandwidth, and the number of input/output nodes thereof increase. Thus, it becomes more important to effectively control the operating frequency, to increase the efficiency of a channel, and to effectively use the input/output nodes.
In order to keep up with such demands, simultaneous bi-directional (SBD) transmission is suggested. U.S. Pat. No. 6,275,066 has disclosed a conventional SBD buffer. In SBD transmission, signals are simultaneously transmitted and received over one channel. Thus, the channel width of the semiconductor devices is doubled without a change in the operating frequency, and the efficiency of the input/output nodes is also doubled. A simultaneous bi-directional (SBD) buffer is used for SBD transmission in applications such as dynamic random access memory (DRAM), for computer graphics applications, where SBD buffers are connected with one another by using point-to-point links or a cache memory that does not need extension thereof. FIG. 1 shows SBD buffers connected with one another by using point-to-point links.
FIG. 1 is a block diagram showing connections of general SBD buffers.
In FIG. 1, input/output nodes of SBD buffers 10 and 20 are connected with one another by a channel 30, and reference voltages VrefH and VrefL are inputted to each of the SBD buffers 10 and 20.
The SBD buffers 10 and 20 are included in separate semiconductor devices, and the reference voltages VrefH and VrefL are generated by a separate reference voltage generating circuit (not shown).
Data input and output between the SBD buffers 10 and 20 will be described with reference to FIG. 2.
FIG. 2 shows changes in voltage levels of input signals of the SBD buffers 10 and 20 depending on the values of output signals of the SBD buffers 10 and 20 of FIG. 1.
A relationship between the input signals of FIG. 2 and the output signals of the SBD buffers 10 and 20 of FIG. 1 is illustrated in Table 1.
TABLE 1OUT1OUT2IN1IN2Voltage1111VDD1001VDD/20000VSS0110VDD/21111VDD
As shown in Table 1, when output signals OUT1 and OUT2 of the SBD buffers 10 and 20 are 1, input signals IN1 and IN2 are 1, and the voltage levels of the input signals IN1 and IN2 are VDD.
When the output signal OUT1 is 1 and the output signal OUT2 is 0, the input signal IN1 is 0 and the input signal IN2 is 1. Here, the voltage levels of the input signals IN1 and IN2 are VDD/2.
When the output signals OUT1 and OUT2 are both 0, the input signals IN1 and IN2 are both 0, and the voltage levels of IN1 and IN2 are VSS.
As described above, since the SBD buffers 10 and 20 transmit signals through a channel 30 using SBD transmission, the voltage levels of the input signals IN1 and IN2 of the SBD buffers 10 and 20 are selected from among three voltage levels VDD, VDD/2, and VSS depending on the values of the output signals OUT1 and OUT2.
As shown in FIG. 2, the SBD buffers 10 and 20 use the reference voltages VrefH and VrefL to read the input signals. Here, a voltage level of the reference voltage VrefH is 3VDD/4, and a voltage level of the reference voltage VrefL is VDD/4.
Operation of the SBD buffers 10 and 20 will be described with reference to FIG. 3.
FIG. 3 is a circuit diagram of the SBD buffers 10 and 20 of FIG. 1.
As shown in FIG. 3, the SBD buffer 10 includes an output driver 11, a multiplexer 12, and an input receiver 13.
The output driver 11 receives an output data signal OUT and outputs the received output data signal OUT to an input/output node IO. The multiplexer 12 outputs one of the reference voltages VrefH and VrefL in response to the output data signal OUT.
When the output data signal OUT is high, the multiplexer 12 outputs the reference voltage VrefH. When the output data signal OUT is low, the multiplexer 12 outputs the reference voltage VrefL.
The input receiver 13 compares the reference voltage VrefH or VrefL with an input signal INO outputted from the input/output node IO and outputs a comparison result.
Operation of the SBD buffer 10 will be described with reference to FIG. 4.
FIG. 4 shows a waveform of input data signals inputted to the input/output node IO of the SBD buffer 10 of FIG. 3.
As shown in FIG. 4, when the output data signal OUT of the SBD buffer 10 is high, that is, the voltage level of the output data signal OUT is VDD, the multiplexer 12 outputs the reference voltage VrefH.
Since the output data signal OUT is high, i.e., the voltage level of the output data signal OUT is VDD, if an input data signal DATA inputted to the input/output node IO is high, the input signal INO inputted to the input receiver 13 is high. When the output data signal OUT is high, i.e., the voltage level of the output signal OUT is VDD, if the input data signal data is low, i.e., VSS, the input data signal is mid level, i.e., VDD/2.
The input receiver 13 compares the input signal INO which is a high level or a mid level, i.e., VDD/2, with the reference voltage VrefH and outputs the comparison result.
Therefore, as indicated by “A” in FIG. 4, the range of the voltage level of the input signal INO is from VDD to VDD/2.
In the meantime, when the output data signal OUT is low, i.e., VSS, the multiplexer 12 outputs the reference voltage VrefL.
When the output data signal OUT is low, if the input data signal DATA inputted to the input/output node IO is high, the input signal INO inputted to the input receiver 13 is a mid level, i.e., VDD/2. When the output data signal OUT is low, if the input data signal DATA is low, i.e., VSS, the input signal INO inputted to the input receiver 13 is low, i.e., VSS.
The input receiver 13 compares the input data signal INO, which is at the mid level, i.e., VDD/2, or at the low level, i.e., VSS, with the reference voltage VrefL and outputs the comparison result.
Therefore, as indicated by “B” in FIG. 4, a range of the voltage level of the input signal INO is from VDD/2 to VSS. Thus, the SBD buffers 10 and 20 can simultaneously output and input data through one channel.
As described above, the SBD buffer makes it possible to simplify a package of a semiconductor device by reducing the channel bandwidth and the number of pins of a semiconductor chip. However, test equipment manufactured by using the SBD buffer_is needed to test the semiconductor device. In addition, the test equipment has to be manufactured by using a circuit having the same characteristics as an output buffer, i.e., the same output impedance and output current, and the same characteristics as an input buffer, i.e., the same input load and a reference voltage.
A self-test method suggested to solve the problems is shown in FIG. 5.
FIG. 5 is a circuit diagram of an SBD buffer having a conventional self-test circuit.
As shown in FIG. 5, an SBD buffer 40 includes an output driver 41, a first multiplexer 42, an input receiver 43, and a second multiplexer 44.
The output driver 41 receives an output data signal OUT and outputs the received output data signal OUT to an input/output node IO. In response to a control signal REFMOD, the first multiplexer 42 outputs the output data signal OUT or a control signal REFDIR as a reference voltage selection signal REFSEL.
Here, the control signal REFMOD selects one of a test mode and a normal operation mode. The control signal REFMOD is activated when the SBD buffer 40 operates in the test mode and is deactivated when the SBD buffer 40 operates in the normal operation mode. A voltage level of the control signal REFDIR changes into high or low and is the same as the voltage level of the output data signal OUT.
The second multiplexer 44 outputs one of the inputted reference voltages VrefH and VrefL in response to the reference voltage selection signal REFSEL. The second multiplexer 44 outputs the reference voltage VrefH when the reference voltage selection signal REFSEL is high and outputs the reference voltage VrefL when the reference voltage selection signal REFSEL is low.
The input receiver 43 compares an input signal IN2 output from the input/output node IO with the reference voltage VrefH or VrefL and outputs the comparison result.
Here, the input signal IN2 is generated by combining the output data signal OUT with an input signal IN1 inputted from the outside through a pad 45.
Self-testing operations of the SBD buffer circuit are in accordance with the following.
If the control signal REFMOD is activated to initiate the test mode, the first multiplexer 42 outputs the control signal REFDIR as the reference voltage selection signal REFSEL. Here, as the control signal REFDIR changes into high or low and is the same as the voltage level of the output data signal OUT, the voltage level of the reference voltage selection signal REFSEL also changes. As a result, the second multiplexer 44 outputs different reference voltages, based on the voltage level of the reference voltage selection signal REFSEL, in the test mode.
More specifically, the reference voltage selection signal REFSEL controls the second multiplexer 44 such that the second multiplexer 44 outputs the reference voltage VrefH when the output data signal OUT is high and outputs the reference voltage VrefL when the output data signal OUT is low.
The input receiver 43 compares the input data signal IN2 output from the input/output node IO with the reference voltage VrefH or VrefL and outputs the comparison result. Since the input signal IN1 is not inputted to the input/output node IO in the test mode, the input signal IN2 is equal to the output data signal OUT.
The input receiver 43 outputs an input signal IN3 having the same voltage level as that of the output data signal OUT. That is, if the output data signal OUT is high, i.e., VDD, the input signal IN3 is high, i.e., VDD, and if the output data signal OUT is low, i.e., VSS, the input signal IN3 is low, i.e., VSS.
Therefore, since the conventional SBD buffer according to prior art performs self-test by using only its output data signal without using the input data signal from outside, it is impossible to accurately test its performance in a range of whole voltage levels.
FIG. 6 is a waveform of input signals when the SBD buffer of FIG. 5 performs self-test by using only its output data signal without using the input data signal from outside.
As shown in FIG. 6, since the input data signal from outside is not used, the input signal is high if the output data signal OUT is high, and the input signal is low if the output data signal OUT is low.
Since the SBD buffer performs self-test without using the input signal having the mid level, i.e., VDD/2, it is not possible to accurately test its performance. In addition, the voltage levels of the reference voltages VrefH and VrefL change into 3VDD/4 or VDD/4 according to the output data signals, but the voltage level of the input data signal changes into high, i.e., VDD, or low, i.e., DSS, according to the output data signal OUT. As a result, the noise margin of the input data signal in a self-testing operation of the SBD buffer is increased by 3 times that in an actual operation of the SBD buffer.